SMT basic knowledge of the pad structure

Land, the basic building block for surface-mount assembly, used to make a land pattern of the board, ie, a variety of land combinations designed for specific component types. There is nothing more frustrating than designing poor pad structures. When a pad structure is not properly designed, it is difficult, and sometimes impossible, to achieve the desired solder joint. Pad has two words in English: Land and Pad, which can often be used interchangeably; however, Land is a two-dimensional surface feature for surface mountable components, and Pad is a three-dimensional feature for Components of the plug-in. As a general rule, Land does not include plated through-holes (PTH). Bypass is a plated through hole (PTH) that connects different circuit layers. Blind via connects the outermost layer with one or more inner layers, while the buried bypass holes connect only the inner layer.

As noted above, Land Land typically does not include plated through holes (PTHs). The PTH in one pad Land will carry a significant amount of solder during the soldering process, in many cases producing insufficiently soldered solder joints. However, in some cases, component routing density is forced to change to this rule, most notably for chip scale packages (CSPs). With a pitch of 1.0 mm (0.0394 "), it is difficult to route a wire through the" labyrinth "of the pad, creating blind side-by-side vias and microvia within the pad, allowing direct routing to another layer Because these by-pass holes are small and blind, they do not draw as much solder, resulting in little or no effect on solder content.

There are many industrial literature out of the Association Connecting Electronics Industries (IPC), EIA (Electronic Industry Alliance), and JEDEC (Solid State Technology Association), which should be used when designing the pad structure. The main document is the IPC-SM-782, "Surface Mount Design and Land Layout Standards," which provides information on the pad structure used for surface-mount components. The pad structure should conform to IPC-SM-782 when J-STD-001, "Requirements for Soldered Electrical and Electronic Assemblies" and IPC-A-610, "Acceptability of Electronic Assemblies," are used as solder point process standards. If the pads deviate significantly from IPC-SM-782, it will be difficult to achieve solder joints that conform to J-STD-001 and IPC-A-610.

Component knowledge (ie, component structure and mechanical size) is a basic requirement for the design of the pad structure. IPC-SM-782 makes extensive use of two component literature: EIA-PDP-100, Registration and Standard Mechanical Appearance of Electronic Components and JEDEC 95 Publication, Registration and Standard Appearance of Solid and Related Products. Undisputedly, the most important of these documents is the JEDEC 95 publication because it deals with the most complex components. It provides mechanical drawings of all registered and standard profiles of solid components.

JEDEC publication JESD30 (also downloadable free of charge from JEDEC's website) defines the abbreviations for components based on their package features, materials, terminal locations, package types, pinouts and number of terminals. Features, materials, locations, forms, and quantity identifiers are optional.

Package Features: A single or multiple letter prefix that identifies features such as pitch and contour.

Packaging Materials: A one-letter prefix that identifies the main packaging material.

Terminal position: A one-letter prefix that identifies the terminal position relative to the outline of the package.

Package Type: A two-letter mark indicating the package's outline type.

Pin new: a single-letter suffix, confirm the pin form.

Number of terminals: A one, two or three digit suffix indicating the number of terminals.

A simple list of surface mount package identifiers includes:

· E Enlarged spacing (> 1.27 mm)

· F dense pitch (<0.5 mm); limited to QFP components

S shrinking pitch (<0.65 mm); all components except QFP.

· T thin (1.0 mm body thickness)

A simple list of surface mount terminal position identifiers includes:

Dual pins on opposite sides of a square or rectangular package.

The Quad pins are on either side of a square or rectangular package.

Surface Mount A simple list of package type identifiers includes:

CC chip carrier package structure

FP flat pack package structure

GA grid array package structure

· SO small outline package structure

A simple list of surface mount pinout identifiers includes:

· B A straight or spherical pin structure; this is a non-compliant pin form

F A straight pin structure; this is a non-compliant pin form

G a fin-shaped pin structure; this is a compliant pin form

J A "J" -shaped bent lead structure; this is a compliant lead form

N a pinless structure; this is a non-compliant pin form

· S An "S" shaped pin structure; this is a compliant pin form

For example, the abbreviation F-PQFP-G208 describes a 0.5 mm (F) plastic (P) square (Q) planar package (FP), a finned pin (G), and the number of terminals 208.

Detailed tolerance analysis of component and board surface features (ie pad structures, fiducials, etc.) is necessary. IPC-SM-782 explains how to do this analysis. Many components (especially closely spaced components) are designed in strict metric units. Do not design an inch pad structure for a metric component. The cumulative structural error does not match, can not be used for close-spaced components. Remember that 0.65mm equals 0.0256 "and 0.5mm equals 0.0197".